Single level cell programming in a multiple level cell non-volatile memory device

ABSTRACT

A multiple level cell memory array has an area that can be programmed as single level cells. The cells to be programmed are initially programmed with the desire data into either the least significant or most significant bit of the cell. A second programming operation the programs reinforcing data that adjusts the threshold level of the cell to the appropriate level for the desired data.

RELATED APPLICATION

This application is a Continuation of U.S. application Ser. No. 11/298,013 titled “SINGLE LEVEL CELL PROGRAMMING IN A MULTIPLE LEVEL CELL NON-VOLATILE MEMORY DEVICE,” filed Dec. 9, 2005 now U.S. Pat. No. 7,366,013 (Allowed), which is commonly assigned and incorporated herein by reference.

TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to memory devices and in particular the present invention relates to non-volatile memory devices.

BACKGROUND OF THE INVENTION

Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.

Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.

As the performance and complexity of electronic systems increase, the requirement for additional memory in a system also increases. However, in order to continue to reduce the costs of the system, the parts count must be kept to a minimum. This can be accomplished by increasing the memory density of an integrated circuit.

Memory density can be increased by using multiple level cells (MLC). MLC memory can increase the amount of data stored in an integrated circuit without adding additional cells and/or increasing the size of the die. The MLC method stores two or more data bits in each memory cell.

MLC requires tight control of the threshold voltages in order to use multiple threshold levels per cell. One problem with non-volatile memory cells that are closely spaced, and MLC in particular, is the floating gate-to-floating gate capacitive coupling that causes interference between cells. The interference can shift the threshold voltage of neighboring cells as one cell is programmed. This is referred to as a program disturb condition that affects cells that are not desired to be programmed.

An MLC memory device also has a lower reliability than a single level cell (SLC) memory device due, in part, to the increased quantity of states requiring more closely spaced threshold voltages. A bad bit in a memory device used to store photographs can be tolerated more easily than a bad bit in a memory device that stores code. A bad bit in a photograph might only produce a bad pixel out of millions of pixels while a bad bit in code or other data could mean a corrupted instruction that affects the operation of an entire program.

Due to intense competition and consumer desire for longer battery life in electronic devices, manufacturers must constantly find ways to reduce the quantity of components in devices while maintaining reliability. For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory device having high density with high reliability.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a simplified diagram of one embodiment for a NAND flash memory array of the present invention.

FIG. 2 shows a diagram of one embodiment of a threshold voltage distribution for a multiple level cell memory array.

FIG. 3 shows a diagram of one embodiment of a simplified memory array in accordance with the programming method of the present invention.

FIG. 4 shows a flow chart of one embodiment of a method of the present invention for single level cell programming of a multiple level cell memory device.

FIG. 5 shows a flow chart of one embodiment of a method for implementation of the single level cell programming method of the present invention in a memory system.

FIG. 6 shows a block diagram of one embodiment of the memory system of the present invention.

FIG. 7 shows a block diagram of one embodiment of a memory module of the present invention.

FIG. 8 shows a block diagram of one embodiment of software modules of the present invention for programming/reading a non-volatile memory integrated circuit.

DETAILED DESCRIPTION

In the following detailed description of the invention, reference is made to the accompanying drawings that form a part hereof and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and equivalents thereof.

FIG. 1 illustrates a simplified diagram of one embodiment for a semiconductor NAND flash memory array of the present invention. This memory array is for purposes of illustration only as the present invention is not limited to any one non-volatile memory technology or architecture.

The memory array of FIG. 1, for purposes of clarity, does not show all of the elements typically required in a memory array. For example, only two bit lines are shown (BL1 and BL2) when the number of bit lines required actually depends upon the memory density and chip architecture. The bit lines are subsequently referred to as (BL1-BLN). The bit lines (BL1-BLN) are eventually coupled to sense amplifiers (not shown) that detect the state of each cell.

The array is comprised of an array of floating gate cells 101 arranged in series strings 104, 105. Each of the floating gate cells 101 are coupled drain to source in each series chain 104, 105. A word line (WL0-WL31) that spans across multiple series strings 104, 105 is coupled to the control gates of every floating gate cell in a row in order to control their operation. In one embodiment, an array is comprised of 32 word lines. However, the present invention is not limited to any one word line quantity.

In operation, the word lines (WL0-WL31) select the individual floating gate memory cells in the series chain 104, 105 to be written to or read from and operate the remaining floating gate memory cells in each series string 104, 105 in a pass through mode. Each series string 104, 105 of floating gate memory cells is coupled to a source line 106 by a source select gate 116, 117 and to an individual bit line (BL1-BLN) by a drain select gate 112, 113. The source select gates 116, 117 are controlled by a source select gate control line SG(S) 118 coupled to their control gates. The drain select gates 112, 113 are controlled by a drain select gate control line SG(D) 114.

In the embodiment of FIG. 1, WL0 is at the bottom of the page and WL31 is at the top of the page. However, these labels are for purposes of illustration only as WL0 can also begin at the top of the page with the word line numbers increasing towards the bottom of the page.

Each cell can be programmed as a single bit per cell (i.e., single level cell—SLC) or multiple bits per cell (i.e., multiple level cell—MLC). Each cell's threshold voltage (V_(t)) determines the data that is stored in the cell. For example, in a single bit per cell, a V_(t) of 0.5V might indicate a programmed cell (i.e., logical 0 state) while a V_(t) of −0.5V might indicate an erased cell (i.e., logical 1 state).

A multilevel cell has multiple V_(t) windows that each indicate a different state. Multilevel cells take advantage of the analog nature of a traditional flash cell by assigning a bit pattern to a specific voltage range stored on the cell. This technology permits the storage of two or more bits per cell, depending on the quantity of voltage ranges assigned to the cell.

For example, a cell may be assigned four different voltage ranges of 200 mV for each range. Typically, a dead space or margin of 0.2V to 0.4V is between each range. If the voltage stored on the cell is within the first range, the cell is storing a 11. If the voltage is within the second range, the cell is storing a 01. This continues for as many ranges that are used for the cell. In one embodiment, 11 is the most negative threshold voltage range while 10 is the most positive threshold voltage range. Alternate embodiments assign the logical states to different threshold voltage ranges.

The embodiments of the present invention are not limited to two bits per cell. Some embodiments may store more than two bits per cell, depending on the quantity of different voltage ranges that can be differentiated on the cell.

During a typical prior art programming operation, the selected word line for the flash memory cell to be programmed is biased with a series of programming pulses that start at a voltage that, in one embodiment, is greater than 16V with each subsequent pulse voltage increasing incrementally until the cell is programmed or a maximum programming voltage is reached.

A verification operation with a word line voltage of 0V is then performed to determine if the floating gate is at the proper voltage (e.g., 0.5V). The unselected word lines for the remaining cells are typically biased at approximately 10V during the program operation. In one embodiment, the unselected word line voltages can be any voltage equal to or greater than ground potential. Each of the memory cells is programmed in a substantially similar fashion.

A typical memory block may be comprised of 64 pages of single level cells. An MLC memory block is typically comprised of 128 pages. When one of these pages is accessed in a typical prior art read/program operation, the remaining pages in the block can experience a disturb condition. In both cases, the pages share common word lines and bitlines that can experience higher programming/read voltages whenever any one of the pages is programmed/read. These voltages can cause problems by disturbing the distributions for the cells that are not being accessed. The embodiments of the present invention, as discussed subsequently, use a scrambled logical addressing technique that substantially reduces or eliminates the disturb condition.

FIG. 2 illustrates a diagram of one embodiment of an MLC threshold voltage distribution in accordance with the programming method of the present invention. This diagram shows that the logical 11 state 201 is the most negative state and the logical 10 state 202 is the most positive state. The 01 state 203 and the 00 state 204 are located between the most distant states 201, 202.

FIG. 3 illustrates a write pattern to a simplified memory array using the single level programming embodiments of the present invention. For purposes of clarity, only four physical rows with two physical bits in each row are shown. The portion of the MLC memory array chosen to be programmed as SLC memory may be one or more memory blocks.

The numbers shown in each cell 301-308 represent the logical page numbers that are written to each particular cell 301-308. This particular pattern was chosen to minimize the floating gate-to-floating gate coupling that occurs when cells are programmed. The present invention, however, is not limited to any one programming pattern.

Each physical cell 301-308 is capable of holding two logical bits, as described previously regarding programming of MLC. Therefore, the addressing scheme of the present invention assigns two scrambled, logical addresses to each physical address. In other words, to increase the noise margin, no physical cell 301-308 in the SLC area of the array has two adjacent logical addresses.

In the illustrated embodiment, logical pages 0 and 1 are programmed into cells 301, 302. Logical pages 2 and 3 are programmed into cells 303, 304 of row 1. Logical pages 4 and 5 are then programmed into cells 301, 302 of row 0. Logical pages 8 and 9 are programmed into cells 303, 304 of row 1. This pattern is repeated throughout the 128 pages of a memory block that is programmed in an SLC manner.

In order to program a physical cell in an MLC manner, each bit of data/code to be programmed is represented by two logical bits. In one embodiment, a logical 11 is assigned to represent a single level bit of 1 while a logical 10 is assigned to represent a single level bit of 0. This data pattern was chosen since the present embodiment of MLC memory, the threshold voltage of 11 is the most negative and the threshold voltage of 10 is the most positive thus substantially reducing the floating gate-to-floating gate interference and increasing the noise margin. Alternate embodiments may use other states besides logical 11 and/or 10.

FIG. 4 illustrates a flow chart of one embodiment of a method of the present invention for single level cell programming of a multiple level cell memory device. For purposes of clarity, only the programming of one cell (e.g., cell 301 of FIG. 3) will be described. The programming of the remainder of the SLC memory block is accomplished in a substantially similar manner. The following discussion refers to both FIGS. 3 and 4.

The data to be stored 401 is received. In one embodiment, as described subsequently with reference to FIG. 5, the received data includes an indication that it is code that requires the more reliable SLC programming of the present invention as opposed to the MLC programming performed for data not requiring the higher reliability.

In one embodiment, the LSB of the cell to be programmed is programmed first 403. However, an alternate embodiment may program the MSB first and the LSB last.

In the illustrated embodiment, the method first programs page 0 into the cell 301 (i.e., LSB). If the cell started from the erased state (i.e., a logical 11) and the data/code bit is a logical 0, then the cell 301 now has a programmed pattern of a logical 10.

When page 4 is to be programmed into the cell 301, it must be done so as to reinforce the desired data/code bit of 0. The reinforcing data is that data which changes the threshold voltage of each SLC programmed cell to the appropriate threshold voltage required for the desire single level data. Therefore, the reinforcing data must be determined 405 and then written into the cell 407. In the present example, a logical 10 is assigned to represent an SLC data bit of logical 0, so the cell is already at the proper threshold voltage. Therefore, when the cell is read, the threshold voltage to which logical 10 state is assigned will be detected and a logical 0 is read.

The above-described example, for purposes of clarity, does not discuss the programming of pages 1-3. By referring to FIGS. 2-4, it can be seen that the other pages are programmed in substantially the same manner.

As another example, if a data/code bit of logical 0 is desired to be programmed into the cell 301 and the cell 301 has already been programmed from a previous page write operation with a logical 01, page 0 of the cell needs to program a logical 0 into the LSB of the cell 301. This is accomplished by raising the threshold voltage of the cell 301 from the logical 01 state to the level of the logical 10 state as seen in FIG. 2. This assumes that the logical 10 state of MLC is equivalent to the logical 0 state of SLC.

FIG. 5 illustrates a flow chart of one embodiment of a method for implementation of the single level cell programming method of the present invention in a multiple level cell memory system. The method determines 501 if the data to be written is code that requires a higher reliability storage or other data that can tolerate the lower reliability of MLC programming.

This determination can be accomplished in various ways. In one embodiment, the physical address indicates whether the user is writing to an SLC area of memory or an MLC area. For example, an address that is in the first 32 MB of the memory array address space can be set aside for SLC data while the remainder of the array address space is MLC data. In such an embodiment, when the data is read, it is assumed that the multiple bits that are read map to a single level data bit.

In another embodiment, an indicator bit is included with the data to dynamically indicate whether to use the SLC driver or the normal MLC programming method. Alternate embodiments can use other forms to identify the type of programming.

The SLC driver 505 has been described with reference to FIGS. 3 and 4. This routine can be executed by the memory integrated circuit control circuitry such as a state machine, processor, or other controller. The normal MLC programming 503 has been described previously with reference to FIG. 1.

FIG. 6 illustrates a functional block diagram of a memory device 600 that can incorporate the flash memory array and programming method embodiments of the present invention. The memory device 600 is coupled to a processor 610 that is responsible for executing the software driver of the present invention for writing SLC data into an MLC device. The processor 610 may be a microprocessor or some other type of controlling circuitry. The memory device 600 and the processor 610 form part of a memory system 620. The memory device 600 has been simplified to focus on features of the memory that are helpful in understanding the present invention.

The processor 610 is coupled to the system memory 680. This memory block 680 includes all of the memory required by the system such as RAM, ROM, magnetic storage drives, or other forms of memory. A memory system may have any one of these types of system memory or all of them. In one embodiment, the low-level software driver of the present invention that enables SLC storage in MLC memory is stored in this system memory 680. The driver may be part of the system 620 operating system that is stored on a hard drive or ROM and eventually read into RAM for execution. The software modules illustrated in FIG. 8 and discussed subsequently show one possible configuration for the software driver of the present invention.

The memory device includes an array of flash memory cells 630 as described above with reference to FIG. 6. The memory array 630 is arranged in banks of rows and columns. The control gates of each row of memory cells is coupled with a word line while the drain and source connections of the memory cells are coupled to bitlines. As is well known in the art, the connections of the cells to the bitlines determines whether the array is a NAND architecture, an AND architecture, or a NOR architecture.

An address buffer circuit 640 is provided to latch address signals provided on address input connections A0-Ax 642. Address signals are received and decoded by a row decoder 644 and a column decoder 646 to access the memory array 630. It will be appreciated by those skilled in the art, with the benefit of the present description, that the number of address input connections depends on the density and architecture of the memory array 630. That is, the number of addresses increases with both increased memory cell counts and increased bank and block counts.

The memory device 600 reads data in the memory array 630 by sensing voltage or current changes in the memory array columns using sense/buffer circuitry 650. The sense/buffer circuitry, in one embodiment, is coupled to read and latch a row of data from the memory array 630. Data input and output buffer circuitry 660 is included for bi-directional data communication over a plurality of data connections 662 with the controller 610. Write circuitry 655 is provided to write data to the memory array.

Control circuitry 670 decodes signals provided on control connections 672 from the processor 610. These signals are used to control the operations on the memory array 630, including data read, data write (program), and erase operations. The control circuitry 670 may be a state machine, a sequencer, or some other type of controller.

The flash memory device illustrated in FIG. 6 has been simplified to facilitate a basic understanding of the features of the memory. A more detailed understanding of internal circuitry and functions of flash memories are known to those skilled in the art.

FIG. 7 is an illustration of an exemplary memory module 700. Memory module 700 is illustrated as a memory card, although the concepts discussed with reference to memory module 700 are applicable to other types of removable or portable memory, e.g., USB flash drives, and are intended to be within the scope of “memory module” as used herein. In addition, although one example form factor is depicted in FIG. 7, these concepts are applicable to other form factors as well.

In some embodiments, memory module 700 will include a housing 705 (as depicted) to enclose one or more memory devices 710, though such a housing is not essential to all devices or device applications. At least one memory device 710 is a non-volatile memory [including or adapted to perform elements of the invention]. Where present, the housing 705 includes one or more contacts 715 for communication with a host device. Examples of host devices include digital cameras, digital recording and playback devices, PDAs, personal computers, memory card readers, interface hubs and the like. For some embodiments, the contacts 715 are in the form of a standardized interface. For example, with a USB flash drive, the contacts 715 might be in the form of a USB Type-A male connector. For some embodiments, the contacts 715 are in the form of a semi-proprietary interface, such as might be found on COMPACTFLASH memory cards licensed by SANDISK Corporation, MEMORYSTICK memory cards licensed by SONY Corporation, SD SECURE DIGITAL memory cards licensed by TOSHIBA Corporation and the like. In general, however, contacts 715 provide an interface for passing control, address and/or data signals between the memory module 700 and a host having compatible receptors for the contacts 715.

The memory module 700 may optionally include additional circuitry 720 which may be one or more integrated circuits and/or discrete components. For some embodiments, the additional circuitry 720 may include a memory controller for controlling access across multiple memory devices 710 and/or for providing a translation layer between an external host and a memory device 710. For example, there may not be a one-to-one correspondence between the number of contacts 715 and a number of I/O connections to the one or more memory devices 710. Thus, a memory controller could selectively couple an I/O connection (not shown in FIG. 7) of a memory device 710 to receive the appropriate signal at the appropriate I/O connection at the appropriate time or to provide the appropriate signal at the appropriate contact 715 at the appropriate time. Similarly, the communication protocol between a host and the memory module 700 may be different than what is required for access of a memory device 710. A memory controller could then translate the command sequences received from a host into the appropriate command sequences to achieve the desired access to the memory device 710. Such translation may further include changes in signal voltage levels in addition to command sequences.

The additional circuitry 720 may further include functionality unrelated to control of a memory device 710 such as logic functions as might be performed by an ASIC (application specific integrated circuit). Also, the additional circuitry 720 may include circuitry to restrict read or write access to the memory module 700, such as password protection, biometrics or the like. The additional circuitry 720 may include circuitry to indicate a status of the memory module 700. For example, the additional circuitry 720 may include functionality to determine whether power is being supplied to the memory module 700 and whether the memory module 700 is currently being accessed, and to display an indication of its status, such as a solid light while powered and a flashing light while being accessed. The additional circuitry 720 may further include passive devices, such as decoupling capacitors to help regulate power requirements within the memory module 700.

FIG. 8 illustrates a block diagram of software modules of the present invention for programming memory devices. The modules are comprised of a flash translation layer (FTL) 801 and at least one low-level software driver 802. While only one low-level driver 802 is shown in FIG. 8, it is well known in the art that a memory system may have multiple such drivers.

The high-level driver 801 works in conjunction with an operating system or an application to manage a flash memory integrated circuit. The FTL 801 manages data in a flash device so that it appears that the data is written to a particular location when in fact the data is being stored in different locations of the flash. The FTL 801 moves the data to different physical locations in the flash memory array in order to achieve more even wear characteristics. This allows the flash device to appear as a disk drive or other block storage device to the processor.

The low-level drivers 802 are responsible for taking the remapped addresses and data from the FTL 801 and performing the actual programming/reading of the data. In one embodiment, the embodiments of the SLC programming in an MLC flash memory device are performed by a low-level memory driver.

CONCLUSION

In summary, the embodiments of the present invention create an MLC non-volatile memory device with at least one SLC memory cell in the same memory array as a plurality of MLC data. The programming/reading of SLC data in the MLC device is determined dynamically by control circuit/processor executing a low-level software driver in response to data reliability or address. This gives the end user of the MLC non-volatile memory device the option of storing sensitive code data in the SLC area for higher reliability and other, less sensitive data in the denser MLC area of the array.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the invention will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the invention. It is manifestly intended that this invention be limited only by the following claims and equivalents thereof. 

1. A method for single level programming in a multiple level memory cell, the method comprising: writing single level data to one of a plurality of bits of the memory cell; and writing reinforcing data to the remaining plurality of bits of the memory cell such that a threshold voltage of the memory cell is adjusted to one of two desired threshold voltages representing the single level data.
 2. The method of claim 1 wherein the one of the plurality of bits is a least significant bit of the memory cell.
 3. The method of claim 1 wherein the one of the plurality of bits is a most significant bit of the memory cell.
 4. The method of claim 1 wherein the one of the plurality of bits is not a least or a most significant bit of the memory cell.
 5. The method of claim 1 wherein the single level data is accompanied by an indicator bit identifying data as single level or multilevel data.
 6. The method of claim 5 further comprising storing data as single level data or multilevel data in the multilevel memory cell in response to the indicator bit.
 7. A method for programming single level data in a multilevel memory cell, comprising: assigning a first memory cell level to represent single level data having a first level; assigning a second memory cell level to represent single level data having a second level wherein a third memory cell level exists between the first memory cell level and the second memory cell level; and programming the memory cell to one of the first or second memory cell levels representative of the level of the single level data.
 8. The method of claim 7 wherein the first memory cell level represents an erased state of the memory cell.
 9. The method of claim 7 further comprising assigning the first memory cell level to represent a most negative threshold level of the memory cell.
 10. The method of claim 7 further comprising assigning the second memory cell level to represent a most positive threshold level of the memory cell.
 11. The method of claim 7 further comprising programming data to the memory cell as single level data in response to an indicator bit identifying the data as single level data.
 12. The method of claim 11 further comprising programming data in the memory cell as multilevel data in response to the indicator bit identifying the data as multilevel data.
 13. The method of claim 7 further comprising reading the memory cell and mapping the read data to the first level of single level data if the memory cell is programmed to the first memory cell level and mapping the read data to the second level of single level data if the memory cell is programmed to the second memory cell level.
 14. A method for programming a single bit of data in a multilevel memory cell having more than two data states wherein each data state is represented by a range of threshold voltages of the memory cell, comprising: programming the multilevel cell to only one of two data states of the more than two data states such that a first data state of the more than two data states represents a most negative threshold voltage of the memory cell and a second data state of the more than two data states represents a most positive threshold voltage of the memory cell.
 15. The method of claim 14 wherein one or more data states exist between the first and second data states.
 16. A method for programming an array of multilevel cells with multilevel and single level data wherein the data is represented by a plurality of bits each bit representing a level, comprising: programming single level data to a multilevel cell by programming one bit of the multilevel cell to one of two threshold levels such that the two threshold levels comprise the least and greatest threshold levels of the memory cell; programming multilevel data to a memory cell by programming the cell to one of a plurality of levels wherein each level is representative of the multilevel data; and programming a least significant bit of the multilevel data to a memory cell and a most significant bit of the multilevel data to a different memory cell.
 17. A memory device, comprising: an array of multilevel memory cells each memory cell configured to store multilevel data comprising a plurality of bits of data wherein each bit has a logical address; and control circuitry configured to program each logical address to a different memory cell of the array of memory cells such that no adjacent logical addresses are stored in the same memory cell; and wherein the control circuitry is further configured to determine if data to be stored is one of single level data and multilevel data and to program single level data to a memory cell to one of two levels such that the two levels comprise a least and a greatest threshold potential of the memory cell wherein at least a third level is present between the two levels and program multilevel data to a memory cell to a threshold potential representative of the multilevel data.
 18. The memory device of claim 17 wherein the data to be stored comprises an indicator having a state which indicates that the data is one of either single level data or multilevel data.
 19. The memory device of claim 18 wherein the control circuitry determines if the data is one of either single level data or multilevel data in response to the state of the indicator.
 20. The memory device of claim 18 wherein the indicator comprises an indicator bit. 